Architecture for Flow Control and Input Buffering on High Speed Interfaces

A fundamental component of high-speed optical fiber networks is a low cost, high bandwidth interface for the network processors. These interface buses use some form of input buffering on their ingress path. Traditional communication ASICs used per-port FIFO queues for this input buffering. With the increasing number of ports supported by newer interfaces, this form of static allocation becomes impractical due to excessively large buffer requirement. In this paper, we propose a new credit based flow control scheme and a buffer management architecture, which is based on dynamic allocation of buffer space from a shared memory pool. We present the advantages, which allow our scheme to overcome problems associated with existing input buffering methods. We show that as the number of ports increases the performance advantage offered by our architecture is better than traditional schemes. A linked list based implementation of the dynamic allocation architecture is also illustrated. Introduction High-bandwidth low-latency communication between network devices is critical to the ability of a network communication system to achieve high performance. Packet Over SONET/SDH (POS) enables network core routers to send native IP packets directly over SONET/SDH frames. POS provides lower packet overhead and lower cost per Mbit than any other data transport method. These efficiencies, along with the rapid evolution of the optical network, enable POS to efficiently support increases in IP traffic over existing and new fiber networks. One of the most critical electrical interfaces in data switching and routing systems is the System Packet Interface (SPI) [1]. The System Packet Interface specifies a point-to-point link between Physical Layer (PHY) device(s) and the rest of the SONET/SDH System (i.e. between the SONET/SDH Framer and the Link Layer). This interface separates the synchronous PHY layer from the asynchronous packet-based processing performed by the higher layers. As such, the SPI supports transmit and receive data transfers at clock rates independent of the actual line bit rate. It is designed for the efficient transfer of both variable-sized packet and fixed-sized cell data [1]. Figure 1 shows the model of an SPI bus. The fundamental requirement of the bus is to transfer data from ports on the source device to the corresponding ports on the sink device. The receptor of data (The sink) indicates the availability of space in its port FIFOs to the initiator of data transfer (The source). Source selects a particular port and initiates transfer on the bus based on the occupancy status feedback from the sink and the availability of data for that port in its local port FIFOs. The source’s selection policy and sink’s status indication policy are implementation specific. Source FIFO Source interface Sink interface Sink FIFO data